1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which noise of power voltage and ground voltage lines is prevented, thereby supplying a stable power voltage to an internal circuit, and a layout method of a decoupling a capacitor thereof.
2. Description of the Related Art
To satisfy high performance and high speed operation requirements of an electronic device system, a semiconductor integrated circuit becomes more complicated in configuration, and an operation speed of the semiconductor integrated circuit becomes faster. As a circuit for constituting a semiconductor device is complicated, parasite capacitance, inductance and resistance are increased, and so measures for noise of power voltage and ground voltage lines to supply a stable power voltage to an internal circuit of a semiconductor device become an important issue.
One conventional measure for noise of the power voltage and ground voltage lines is a method for installing a capacitor, called a decoupling capacitor, between the power voltage line and an internal circuit, e.g., driver circuit to use the capacitor as a temporary current source. That is, the decoupling capacitor supplies the internal circuit with a transient large current necessary when a clock of the internal circuit transitions from one state to the other state, so that abrupt flow of the electric current to the internal circuit from a power supply is prevented, thereby preventing noise induced to the power voltage line and a voltage drop.
Meanwhile, high integration of a semiconductor device has been advanced by a photolithography technique. The photolithography is a process for shifting a pattern of a geometrical shape on a mask onto a thin layer of a photo sensitive material, i.e., photo resist which covers a semiconductor wafer surface.
High integration of a semiconductor device has been also advanced by an etching technique (e.g., plasma technique and reactive ion etching (RIE) technique). The etching technique has a disadvantage in that charges which cause a defect of a gate insulating layer are accumulated in a floated gate and so a plasma damage phenomenon occurs where a function of the gate insulating layer is seriously degraded, whereby reliability and characteristics of a semiconductor device are degraded due to accumulation of charges.
That is, serious charging damage occurs in the gate insulating layer since high density plasma is used and so a strong electric field is formed between a gate and a substrate of a semiconductor device. In a high density plasma process, particles of a plasma state comprise a neutral atom or molecule which occupies a predetermined percentage, an electron with a negative charge, a cation with a positive charge, and an anion with a negative charge.
Plasma is affected by an externally applied electric field or magnetic field due to the existence of such electric charge particles, and the electric charge particles are connected by electrical force which works between the electric charge particles in addition to a collision between particles in gas, so that a large number of particles move in mass.
A quantitative analyzing method of plasma damage is possible by adding an antenna pattern to a semiconductor device, e.g., a gate of a decoupling capacitor which is a MOS capacitor to accelerate charge reduction of the MOS capacitor and by measuring a characteristic variation of the MOS capacitor. In the plasma process, the antenna pattern serves as a feeler for collecting charges induced during the process, and so it is called an antenna.
At this time, a diode junction for performing an antenna function is used to prevent plasma damage, and electrons which move to a stepped portion of a gate oxide layer are reduced such that one end of the diode junction is connected to a ground voltage and the other end is connected to a gate electrode, and electrons distributed in the gate electrode are grounded.
If the antenna diode junction is not inserted into the decoupling capacitor, the gate oxide layer can be cracked by anions generated in the etching process.
FIG. 1 is a layout diagram illustrating a part of a conventional decoupling capacitor. The decoupling capacitor of FIG. 1 comprises a plurality of active regions 10-1 to 10-A, a plurality of antenna diode junctions 30-1 to 30-C, and a plurality of gate poly layers 20-1 to 20-B.
The plurality of active regions 10-1 to 10-A are arranged in a transverse direction by diffusing an n-type impurity into a p-type semiconductor substrate, and a plurality of antenna diode junctions 30-1 to 30-C are arranged between the plurality of active regions 10-1 to 10-A by diffusing an n-type impurity into portions of the semiconductor substrate where the active regions are not diffused.
The plurality of gate poly layers 20-1 to 20-B are arranged in a longitudinal direction on portions of the semiconductor substrate where the plurality of active regions 10-1 to 10-A are diffused by forming a gate region of a transistor on portions of the semiconductor substrate where the plurality of antenna diode junctions 30-1 to 30-c are not diffused.
FIG. 2 is a layout diagram illustrating a conventional decoupling capacitor for supplying an electrical power to a semiconductor device. The decoupling capacitor of FIG. 2 comprises a plurality of decoupling capacitor cells 40-1 to 40-L, a plurality of sub voltage supplying lines Vdd-1 to Vdd-m and Vss-1 to Vss-n, a plurality of main voltage supplying lines VDD_S and VSS_S, and a plurality of first and second contacts con1 and con2 (see FIG. 3). The plurality of sub voltage supplying lines Vdd-1 to Vdd-m and Vss-1 to Vss-n comprises a plurality of sub power voltage supplying lines Vdd-1 to Vdd-m and a plurality of sub ground voltage supplying lines Vss-1 to Vss-n, which are made of a metallic material. The plurality of main voltage supplying lines VDD_S and VSS_S comprises a main power voltage supplying line VDD_S and a main ground voltage supplying line VSS_S.
The plurality of decoupling capacitor cells 40-1 to 40-L are arranged adjacent to each other and with up-down symmetry and left-right symmetry to prevent abrupt flow of an electric current to an internal circuit of the semiconductor device from a power supply (not shown), thereby preventing noise induced by a power voltage line and a voltage drop.
The plurality of main voltage supplying lines VDD_S and VSS_S arranged such that first metal lines are disposed on left and right sides of a plurality of decoupling capacitor cells 40-1 to 40-L to be electrically connected to a plurality of decoupling capacitor cells 40-1 to 40-L in order to supply a power voltage and a ground voltage from the power supply to the plurality of decoupling capacitor cells 40-1 to 40-L through power pads.
The plurality of sub power voltage supplying lines Vdd-1 to Vdd-m electrically connect the gate poly layers in a plurality of decoupling capacitor cells 40-1 to 40-L to a plurality of main voltage supplying lines VDD_S and VSS_S through the first and second contacts con1 and con2.
Of course, a structure for arranging second metal lines below or above the first metal lines and electrically connecting them through a plurality of third contacts is possible.
FIG. 3 is a layout diagram illustrating one decoupling capacitor cell of the decoupling capacitor of FIG. 2. The decoupling capacitor cell of FIG. 3 comprises the active region 10-1, the two antenna diode junctions 30-1 and 30-2, the gate poly layer 20-2, the sub power voltage supplying line Vdd-2, the sub ground voltage supplying line Vss-1, and the plurality of first and second contacts con1 and con2.
The active region 10-1 is arranged such that an n-type impurity is diffused into a p-type semiconductor substrate, and the two antenna diode junctions 30-1 and 30-2 are arranged such that an n-type impurity is diffused into an upper center of the semiconductor substrate where the active region 10-1 is not diffused.
The gate poly layer 20-2 is arranged such that a gate region of a transistor is formed on a portion of the semiconductor substrate where the two antenna diode junctions 30-1 and 30-2 are not diffused and is stacked in a rectangular shape on a portion of the semiconductor substrate where the active region 10-1 is diffused.
The sub power voltage supplying line Vdd-2 is stacked in a T shape above the gate poly layer 20-2 of the upper center and the two antenna diode junctions 30-1 and 30-2 of the upper left and right sides and is electrically connected to the gate poly layer 20-2 and the antenna diode junctions 30-1 and 30-2 through the plurality of first contacts con1 and the plurality of second contacts con2.
The sub ground voltage supplying line Vss-1 is arranged such that it is stacked in a rectangular shape whose upper portion is cut out (i.e., in a “u” shape) above the active regions 10-1 and its left and right sides are electrically connected to the active regions 10-1 via the plurality of second contacts 2.
FIG. 4 is a cross-sectional view taken along line A-A′ of FIG. 3. The p-type semiconductor substrate 5, the two antenna diode junctions 30-1 and 30-2, a gate oxide layer 15, the gate poly layer 20-2, the sub power voltage supplying line Vdd-2, some of the plurality of first and second contacts con1 and con2, and an insulating layer 35 are provided.
FIG. 5 is a cross-sectional view taken along line B-B′ of FIG. 3. The p-type semiconductor substrate 5, the two n-type active regions 10-1, the gate oxide layer 15, the gate poly layer 20-2, the sub power voltage supplying line Vdd-2, the sub ground voltage supplying line Vss-1, others of the plurality of second contacts con2, and the insulating layer 35 are provided.
Here, FIG. 5 shows the two n-type active regions 10-1, the sub ground voltage supplying line Vss-1, and the second contacts con2, which are not shown in FIG. 4, and the p-type semiconductor substrate 5, the gate oxide layer 15, the gate poly layer 20-2, and the insulating layer 35 of FIG. 5, which are also shown in FIG. 4, and thus a cross-sectional structure of the decoupling capacitor cell is described below with reference to FIGS. 4 and 5.
In FIG. 4, the two antenna diode junctions 30-1 and 30-2 are n-type impurity diffusing layers and are formed on both upper left and right sides of the p-type semiconductor substrate 5, and the gate poly layer 20-2 is stacked on an upper center of the p-type semiconductor substrate 5 where the antenna diode junctions 30-1 and 30-2 and the n-type active regions 10-1 are not formed.
The gate oxide layer 15 is formed between the gate poly layer 20-2 and the p-type semiconductor substrate 5, and the sub power voltage supplying line Vdd-2 is stacked above the gate poly layer 20-2 and the antenna diode junctions 30-1 and 30-2 and is electrically connected to the gate poly layer 20-2 and the antenna diode junctions 30-1 and 30-2.
In FIG. 5, the two n-type active regions 10-1 are n-type impurity diffusing layers and are formed on upper left and right sides of the p-type semiconductor substrate 5, and the sub ground voltage supplying line Vss-1 is stacked above the two n-type active regions 10-1 and is electrically connected to the two n-type active regions 10-1 via second contacts con2. Here, a plurality of second contacts are used to be distinguished from a plurality of first contacts con1, but the type of contacts used for the first and second contacts can be otherwise identical in a semiconductor device manufacturing process.
A power supplying operation of the conventional decoupling capacitor is described below with reference to FIGS. 1 to 5.
In FIG. 4, the sub power voltage supplying line Vdd-2 is electrically connected to the gate poly layer 20-2 via the plurality of first contacts con1 and is also electrically connected to the two antenna diode junctions 30-1 and 30-2 via the plurality of second contacts con2.
Plasma used in a semiconductor device manufacturing process is generated and maintained by an electric discharge, and such plasma is used in deposition and etching processes of a semiconductor device manufacturing process. In this semiconductor chip structure, the gate oxide layer 15 and the gate poly layer 20-2 can have a stepped portion in a junction portion of field oxides for isolating a semiconductor element.
Due to the shape of the stepped portion of the gate poly layer 20-2, electrons widely distributed in the gate poly layer 20-2 move to the stepped portion to get to the gate oxide layer 15 and get trapped or damaged. As a result, a threshold voltage is shifted, a drain current is reduced, and a lifespan of a gate insulating layer conductance is reduced, whereby it acts as a critical factor for causing an abnormal function of a semiconductor device.
In FIGS. 2 and 3, when the plurality of main voltage supplying lines VDD_S and VSS_S are supplied with a power voltage and a ground voltage through the power pads from a predetermined power supply, the plurality of sub power voltage supplying lines Vdd-1 to Vdd-m and the plurality of sub ground voltage supplying lines Vss-1 to Vss-n, forming a plurality of sub voltage supplying lines, receive the power voltage and the ground voltage and apply them to the plurality of decoupling capacitor cells 40-1 to 40-L.
The plurality of decoupling capacitor cells 40-1 to 40-L are electrically connected to each other, and receive the power voltage and the ground voltage from the plurality of sub voltage supplying lines Vdd-1 to Vdd-m and apply them to adjacent up, down, left and right decoupling capacitor cells through the sub power voltage supplying line Vdd-2, the sub ground voltage supplying line Vss-1, and the gate poly layers 20-1 to 20-B.
That is, the power voltage is transferred to the adjacent left and right decoupling capacitor cells through the sub power voltage supplying lines Vdd-2 and to the adjacent up and down decoupling capacitor cells through the gate poly layers 20-1 to 20-B, whereas the ground voltage is transferred to the adjacent left and right decoupling capacitor cells through the sub ground voltage supplying line Vss-1 to Vss-n. However, the ground voltage is transferred to the adjacent up and down decoupling capacitor cells through a detour using the sub ground voltage supplying lines Vss-1 to Vss-n and the main ground voltage supplying lines VSS_S since the gate poly layers 20-1 to 20-B cannot be used as a medium for transferring the ground voltage to the adjacent up and down decoupling capacitor cells due to insertion of the antenna diode junctions 30-1 to 30-C for preventing a plasma damage phenomenon.
However, if the ground voltage is transferred to the adjacent up and down decoupling capacitor cells through a detour using the sub ground voltage supplying lines Vss-1 to Vss-n and the main ground voltage supplying lines VSS_S as described above, inductance and resistance are increased, resulting in an increment of noise from the ground voltage line, whereby there is a problem in that it is difficult to supply a stable power voltage to the internal circuit of the semiconductor device.